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MX25L3225D
MX25L3225D DATASHEET
P/N: PM1432
1
REV. 0.00, SEP. 19, 2008
MX25L3225D
Contents
FEATURES ................................................................................................................................................................. 5 GENERAL DESCRIPTION ........................................................................................................................................ 7 Table 1. Additional Feature ................................................................................................................................ 7 PIN CONFIGURATIONS ............................................................................................................................................. 8 PIN DESCRIPTION .................................................................................................................................................... 8 BLOCK DIAGRAM ...................................................................................................................................................... 9 DATA PROTECTION ..................................................................................................................................................10 Table 2. Protected Area Sizes ..........................................................................................................................11 Table 3. 4K-bit Secured OTP Definition ............................................................................................................. 11 Memory Organization .............................................................................................................................................. 12 Table 4. Memory Organization ......................................................................................................................... 12 DEVICE OPERATION ................................................................................................................................................ 14 Figure 1. Serial Modes Supported ..................................................................................................................... 14 COMMAND DESCRIPTION ....................................................................................................................................... 15 Table 5. Command Set ..................................................................................................................................... 15 (1) Write Enable (WREN) .................................................................................................................................. 16 (2) Write Disable (WRDI) .................................................................................................................................. 16 (3) Read Identification (RDID) ........................................................................................................................... 16 (4) Read Status Register (RDSR) ..................................................................................................................... 17 (5) Write Status Register (WRSR) ....................................................................................................................18 Table 6. Protection Modes ................................................................................................................................. 18 (6) Read Data Bytes (READ) ............................................................................................................................ 19 (7) Read Data Bytes at Higher Speed (FAST_READ) ....................................................................................... 19 (8) 2 x I/O Read Mode (2READ) .......................................................................................................................19 (9) 4 x I/O Read Mode (4READ) .......................................................................................................................20 (10) Sector Erase (SE) ..................................................................................................................................... 20 (11) Block Erase (BE) ......................................................................................................................................20 (12) Chip Erase (CE) ........................................................................................................................................ 21 (13) Page Program (PP) ...................................................................................................................................21 (14) 4 x I/O Page Program (4PP) ...................................................................................................................... 22 (15) Continuously program mode (CP mode) .....................................................................................................22 (16) Deep Power-down (DP) .............................................................................................................................22 (17) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ................................................. 23
P/N: PM1432
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REV. 0.00, SEP. 19, 2008
MX25L3225D
(18) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) ............................................. 23 Table 7. ID Definitions ....................................................................................................................................... 24 (19) Enter Secured OTP (ENSO) ...................................................................................................................... 24 (20) Exit Secured OTP (EXSO) ........................................................................................................................ 24 (21) Read Security Register (RDSCUR) ........................................................................................................... 24 Table 8. Security Register Definition ................................................................................................................. 25 (22) Write Security Register (WRSCUR) ........................................................................................................... 25 POWER-ON STATE ................................................................................................................................................... 26 ELECTRICAL SPECIFICATIONS .............................................................................................................................. 27 ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 27 CAPACITANCE TA = 25 C, f = 1.0 MHz ........................................................................................................... 27 Figure 2.Maximum Negative Overshoot Waveform ............................................................................................ 27 Figure 3. Maximum Positive Overshoot Waveform ............................................................................................ 27 Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL ............................................................. 28 Figure 5. OUTPUT LOADING .......................................................................................................................... 28 Table 9. DC CHARACTERISTICS (Temperature = -40 C to 85 C for Industrial grade, VCC = 2.7V ~ 3.6V) ....... 29 Table 10. AC CHARACTERISTICS (Temperature = -40 C to 85 C for Industrial grade, VCC = 2.7V ~ 3.6V) .... 30 Timing Analysis ....................................................................................................................................................... 31 Figure 6. Serial Input Timing ............................................................................................................................. 31 Figure 7. Output Timing .................................................................................................................................... 31 Figure 8. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 ..................................................... 32 Figure 9. Write Enable (WREN) Sequence (Command 06) ................................................................................ 32 Figure 10. Write Disable (WRDI) Sequence (Command 04) ............................................................................... 32 Figure 11. Read Identification (RDID) Sequence (Command 9F) ....................................................................... 33 Figure 12. Read Status Register (RDSR) Sequence (Command 05) ................................................................. 33 Figure 13. Write Status Register (WRSR) Sequence (Command 01) ................................................................ 33 Figure 14. Read Data Bytes (READ) Sequence (Command 03) ....................................................................... 34 Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B) .................................................... 34 Figure 16. 2 x I/O Read Mode Sequence (Command BB) ................................................................................. 35 Figure 17. 4 x I/O Read Mode Sequence (Command EB) ................................................................................. 35 Figure 18. 4 x I/O Read enhance performance Mode Sequence (Command EB) ............................................... 36 Figure 19. Page Program (PP) Sequence (Command 02) ................................................................................. 37 Figure 20. 4 x I/O Page Program (4PP) Sequence (Command 38) ................................................................... 37 Figure 21. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD) ....................... 38 Figure 22. Sector Erase (SE) Sequence (Command 20) .................................................................................. 38 Figure 23. Block Erase (BE) Sequence (Command D8) ................................................................................... 38 Figure 24. Chip Erase (CE) Sequence (Command 60 or C7) ............................................................................ 39 Figure 25. Deep Power-down (DP) Sequence (Command B9) .......................................................................... 39 Figure 26. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB) .. 39 Figure 27. Release from Deep Power-down (RDP) Sequence (Command AB) .................................................. 40
P/N: PM1432 REV. 0.00, SEP. 19, 2008
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MX25L3225D
Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF) ............. 40 Figure 29. Power-up Timing .............................................................................................................................. 41 Table 11. Power-Up Timing and VWI Threshold ................................................................................................. 41 INITIAL DELIVERY STATE .............................................................................................................................. 41 RECOMMENDED OPERATING CONDITIONS .......................................................................................................... 42 ERASE AND PROGRAMMING PERFORMANCE ...................................................................................................... 43 LATCH-UP CHARACTERISTICS ............................................................................................................................... 43 ORDERING INFORMATION ...................................................................................................................................... 44 PART NAME DESCRIPTION ..................................................................................................................................... 45 PACKAGE INFORMATION ......................................................................................................................................... 46
P/N: PM1432
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REV. 0.00, SEP. 19, 2008
ADVANCED INFORMATION
MX25L3225D
32M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH
FEATURES
GENERAL * Serial Peripheral Interface compatible -- Mode 0 and Mode 3 * 32M:33,554,432 x 1 bit structure or 16,772,216 x 2 bits (two I/O read mode) structure or 8,388,608 x 4 bits (four I/O read mode) structure * 1024 Equal Sectors with 4K byte each (32Mb) - Any Sector can be erased individually * 64 Equal Blocks with 64K byte each (32Mb) - Any Block can be erased individually * Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations * Latch-up protected to 100mA from -1V to Vcc +1V * Low Vcc write inhibit is from 1.5V to 2.5V PERFORMANCE * High Performance - Fast read - 1 I/O: 104MHz with 8 dummy cycles - 4 I/O: 75MHz with 6 dummy cycles - 2 I/O: 75MHz with 4 dummy cycles - Fast access time: 104MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load) - Serial clock of four I/O read mode : 75MHz (15pF + TTL Load), which is equivalent to 300MHz - Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) - Byte program time: 7us (typical) - Continuously program mode (automatically increase address under word program mode) - Fast erase time: 90ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 25s(typ.) /chip * Low Power Consumption - Low active read current: 25mA(max.) at 104MHz, 20mA(max.) at 66MHz and 10mA(max.) at 33MHz - Low active programming current: 20mA (max.) - Low active erase current: 20mA (max.) - Low standby current: 20uA (max.) * Typical 100,000 erase/program cycles * 10 years data retention SOFTWARE FEATURES * Input Data Format - 1-byte Command code * Advanced Security Features - Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions - Additional 4K bit secured OTP for unique identifier * Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first)
P/N: PM1432
5
REV. 0.00, SEP. 19, 2008
MX25L3225D
* Status Register Feature * Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - Both REMS,REMS2 and REMS4 commands for 1-byte manufacturer ID and 1-byte device ID HARDWARE FEATURES * SCLK Input - Serial clock input * SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode * SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode * WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O read mode * NC/SIO3 - NC pin or serial data Input/Output for 4 x I/O read mode * PACKAGE - 8-pin SOP (200mil) - All Pb-free devices are RoHS Compliant
P/N: PM1432
6
REV. 0.00, SEP. 19, 2008
MX25L3225D
GENERAL DESCRIPTION
The MX25L3225D are 32,554,432 bit serial Flash memory, which is configured as 4,194,304 x 8 internally. When it is in two or four I/O read mode, the structure becomes 16,777,216 bits x 2 or 8,388,608 bits x 4. The MX25L3225D feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output. The MX25L3225D provides sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for Continuously program mode, and erase command is executes on sector (4K-byte), or block (64K-byte), or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 20uA DC current. The MX25L3225D utilizes MXIC's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.
Table 1. Additional Feature
Additional Features Part Name MX25L3225D Protection and Security Flexible Block protection (BP0-BP3) V 4K-bit secured OTP Read Performance 2 I/O Read (75MHz) V 4 I/O Read (75MHz) RES (command : AB hex) 5E (hex) REMS (command : 90 hex) Identifier REMS2 (command : EF hex) REMS4 (command : DF hex) RDID (command: 9F hex)
V
V
C2 5E (hex) C2 5E (hex) C2 5E (hex) C2 5E 16 (hex) (if ADD=0) (if ADD=0) (if ADD=0)
P/N: PM1432
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REV. 0.00, SEP. 19, 2008
MX25L3225D
PIN CONFIGURATIONS
8-PIN SOP (200mil)
PIN DESCRIPTION
DESCRIPTION Chip Select Serial Data Input (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/O read mode) SO/SIO1 Serial Data Output (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/O read mode) SCLK Clock Input WP#/SIO2 Write protection: connect to GND or Serial Data Input & Output (for 4xI/O read mode) NC/SIO3 NC pin (Not connect) or Serial Data Input & Output (for 4xI/O read mode) VCC + 3.3V Power Supply GND Ground SYMBOL CS# SI/SIO0
CS# SO/SIO1 WP#/SIO2 GND
1 2 3 4
8 7 6 5
VCC NC/SIO3 SCLK SI/SIO0
P/N: PM1432
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REV. 0.00, SEP. 19, 2008
MX25L3225D
BLOCK DIAGRAM
Address Generator
X-Decoder
Memory Array
Page Buffer Data Register Y-Decoder SRAM Buffer CS# WP#/SIO2 NC/SIO3 Sense Amplifier
HV Generator
SI/SIO0
Mode Logic
State Machine
SCLK
Clock Generator Output Buffer
SO/SIO1
P/N: PM1432
9
REV. 0.00, SEP. 19, 2008
MX25L3225D
DATA PROTECTION
The MX25L3225D is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. * Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the power-on reset and tPUW (internal timer) may protect the Flash.
* Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. * Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP) command completion - Continuously Program mode (CP) instruction completion - Sector Erase (SE) command completion - Block Erase (BE) command completion - Chip Erase (CE) command completion * Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES). Advanced Security Features: there are some protection and securuity features which protect content from inadvertent write and hostile access. I. Block lock protection - The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The proected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. Please refer to table of "protected area sizes". - The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit. If the system goes into four I/O read mode, the feature of HPM will be disabled.
*
P/N: PM1432
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REV. 0.00, SEP. 19, 2008
MX25L3225D
Table 2. Protected Area Sizes
Status bit BP3 BP2 BP1 BP0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
Protect Level 32Mb 0(none) 1(1block, block 63th) 2(2blocks, block 62th-63th) 3(4blocks, block 60th-63th) 4(8blocks, block 56th-63th) 5(16blocks, block 48th-63th) 6(32blocks, block 32th-63th) 7(64blocks, all) 8(64blocks, all) 9(32blocks, block 0th-31th) 10(48blocks, block 0th-47th) 11(56blocks, block 0th-55th) 12(60blocks, block 0th-59th) 13(62blocks, block 0th-61th) 14(63blocks, block 0th-62th) 15(64blocks, all)
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit one-time program area for setting device unique serial number - Which may be set by factory or system customer. Please refer to table 3. 4K-bit secured OTP definition. - Security register bit 0 indicates whether the chip is locked by factory or not. - To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command. - Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to table of "security register definition" for security register bit definition and table of "4K-bit secured OTP definition" for address range definition. - Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured OTP mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Definition Address range xxx000~xxx00F xxx010~xxx1FF Size 128-bit 3968-bit Standard Factory Lock ESN (electrical serial number) N/A Customer Lock
Determined by customer
P/N: PM1432
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MX25L3225D
Memory Organization
Table 4. Memory Organization
Block 63 Sector 1023 . . . 1008 1007 . . . 992 991 . . . 976 975 . . . 960 959 . . . 944 58 943 . . . 928 57 927 . . . 912 911 . . . 896 895 . . . 880 54 879 . . . 864 53 863 . . . 848 847 . . . 832 831 . . . 816 50 815 . . . 800 49 799 . . . 784 783 . . . 768
P/N: PM1432
62
Address Range 3FF000h 3FFFFFh . . . . . . 3F0000h 3F0FFFh 3EF000h 3EFFFFh . . . . . . 3E0000h 3DF000h . . . 3D0000h 3CF000h . . . 3C0000h 3BF000h . . . 3B0000h 3AF000h . . . 3A0000h 39F000h . . . 390000h 38F000h . . . 380000h 37F000h . . . 370000h 36F000h . . . 360000h 35F000h . . . 350000h 34F000h . . . 340000h 33F000h . . . 330000h 32F000h . . . 320000h 31F000h . . . 310000h 30F000h . . . 300000h 3E0FFFh 3DFFFFh . . . 3D0FFFh 3CFFFFh . . . 3C0FFFh 3BFFFFh . . . 3B0FFFh 3AFFFFh . . . 3A0FFFh 39FFFFh . . . 390FFFh 38FFFFh . . . 380FFFh 37FFFFh . . . 370FFFh 36FFFFh . . . 360FFFh 35FFFFh . . . 350FFFh 34FFFFh . . . 340FFFh 33FFFFh . . . 330FFFh 32FFFFh . . . 320FFFh 31FFFFh . . . 310FFFh 30FFFFh . . . 300FFFh
Block 47
Sector 767 . . . 752 751 . . . 736 735 . . . 720 719 . . . 704 703 . . . 688 687 . . . 672 671 . . . 656 655 . . . 640 639 . . . 624 623 . . . 608 607 . . . 592 591 . . . 576 575 . . . 560 559 . . . 544 543 . . . 528 527 . . . 512
46
Address Range 2FF000h 2FFFFFh . . . . . . 2F0000h 2F0FFFh 2EF000h 2EFFFFh . . . . . . 2E0000h 2DF000h . . . 2D0000h 2CF000h . . . 2C0000h 2BF000h . . . 2B0000h 2AF000h . . . 2A0000h 29F000h . . . 290000h 28F000h . . . 280000h 27F000h . . . 270000h 26F000h . . . 260000h 25F000h . . . 250000h 24F000h . . . 240000h 23F000h . . . 230000h 22F000h . . . 220000h 21F000h . . . 210000h 20F000h . . . 200000h 2E0FFFh 2DFFFFh . . . 2D0FFFh 2CFFFFh . . . 2C0FFFh 2BFFFFh . . . 2B0FFFh 2AFFFFh . . . 2A0FFFh 29FFFFh . . . 290FFFh 28FFFFh . . . 280FFFh 27FFFFh . . . 270FFFh 26FFFFh . . . 260FFFh 25FFFFh . . . 250FFFh 24FFFFh . . . 240FFFh 23FFFFh . . . 230FFFh 22FFFFh . . . 220FFFh 21FFFFh . . . 210FFFh 20FFFFh . . . 200FFFh
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61
45
60
44
59
43
42
41
56
40
55
39
38
37
52
36
51
35
34
33
48
32
12
MX25L3225D
Block 31 Sector 511 . . . 496 495 . . . 480 479 . . . 464 463 . . . 448 447 . . . 432 26 431 . . . 416 25 415 . . . 400 399 . . . 384 383 . . . 368 22 367 . . . 352 21 351 . . . 336 335 . . . 320 319 . . . 304 18 303 . . . 288 17 287 . . . 272 271 . . . 256 Address Range 1FF000h 1FFFFFh . . . . . . 1F0000h 1F0FFFh 1EF000h 1EFFFFh . . . . . . 1E0000h 1DF000h . . . 1D0000h 1CF000h . . . 1C0000h 1BF000h . . . 1B0000h 1AF000h . . . 1A0000h 19F000h . . . 190000h 18F000h . . . 180000h 17F000h . . . 170000h 16F000h . . . 160000h 15F000h . . . 150000h 14F000h . . . 140000h 13F000h . . . 130000h 12F000h . . . 120000h 11F000h . . . 110000h 10F000h . . . 100000h 1E0FFFh 1DFFFFh . . . 1D0FFFh 1CFFFFh . . . 1C0FFFh 1BFFFFh . . . 1B0FFFh 1AFFFFh . . . 1A0FFFh 19FFFFh . . . 190FFFh 18FFFFh . . . 180FFFh 17FFFFh . . . 170FFFh 16FFFFh . . . 160FFFh 15FFFFh . . . 150FFFh 14FFFFh . . . 140FFFh 13FFFFh . . . 130FFFh 12FFFFh . . . 120FFFh 11FFFFh . . . 110FFFh 10FFFFh . . . 100FFFh
0 1 10 Block 15 Sector 255 . . . 240 239 . . . 224 223 . . . 208 207 . . . 192 191 . . . 176 175 . . . 160 9 159 . . . 144 143 . . . 128 127 . . . 112 6 111 . . . 96 5 95 . . . 80 79 . . . 64 63 . . . 48 2 47 . . . 32 31 . . . 16 15 . . . 4 3 2 1 0 Address Range 0FF000h 0FFFFFh . . . . . . 0F0000h 0F0FFFh 0EF000h 0EFFFFh . . . . . . 0E0000h 0DF000h . . . 0D0000h 0CF000h . . . 0C0000h 0BF000h . . . 0B0000h 0AF000h . . . 0A0000h 09F000h . . . 090000h 08F000h . . . 080000h 07F000h . . . 070000h 06F000h . . . 060000h 05F000h . . . 050000h 04F000h . . . 040000h 03F000h . . . 030000h 02F000h . . . 020000h 01F000h . . . 010000h 00F000h . . . 004000h 003000h 002000h 001000h 000000h 0E0FFFh 0DFFFFh . . . 0D0FFFh 0CFFFFh . . . 0C0FFFh 0BFFFFh . . . 0B0FFFh 0AFFFFh . . . 0A0FFFh 09FFFFh . . . 090FFFh 08FFFFh . . . 080FFFh 07FFFFh . . . 070FFFh 06FFFFh . . . 060FFFh 05FFFFh . . . 050FFFh 04FFFFh . . . 040FFFh 03FFFFh . . . 030FFFh 02FFFFh . . . 020FFFh 01FFFFh . . . 010FFFh 00FFFFh . . . 004FFFh 003FFFh 002FFFh 001FFFh 000FFFh
30
14
29
13
12
28
11
27
8
24
7
23
4
20
3
19
16
P/N: PM1432
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MX25L3225D
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. 3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge. 4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 2. 5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, 4READ,RES, REMS, REMS2 and REMS4 the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, 4PP, CP, RDP, DP, ENSO, EXSO,and WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
CPOL
CPHA SCLK
shift in
shift out
(Serial mode 0)
0
0
(Serial mode 3)
1
1
SCLK
SI
MSB
SO
MSB
Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported.
P/N: PM1432
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MX25L3225D
COMMAND DESCRIPTION
Table 5. Command Set
CO M M A ND (by te) W RE N (write enable) 06 (hex ) W RDI (write dis able) 04 (hex ) RDID (read RDS R (read W RS R RE A D (read FA S T identific ation) s tatus (write s tatus data) RE A D (fas t regis ter) regis ter) read data) 9F (hex ) 05 (hex ) 01 (hex ) V alues 03 (hex ) A D1(A 23A 16) A D2 (A 15A 8) A D3 (A 7A 0) n by tes read out until CS # goes high 0B (hex ) A D1 A D2 A D3 Dum m y s ets the (W E L) write enable latc h bit res ets the (W E L) write enable latc h bit outputs JE DE C ID: 1by te m anufac turer ID & 2-by te devic e ID to read out the values of the s tatus regis ter to write new values to the s tatus regis ter n by tes read out until CS # goes high n by tes read out by 2 x I/O until CS # goes high n by tes read out by 4 x I/O until CS # goes high 2RE A D (2 x I/O read c om m and) Note1 B B (hex ) A DD(2) A DD(2) & Dum m y (2) 4RE A D (4 x I/O read c om m and) E B (hex ) A DD(4) & Dum m y (4) Dum m y (4)
1s t by te 2nd by te 3rd by te 4th by te 5th by te A c tion
COMMAND 4PP (quad (byte) page program)
1st byte 2nd byte 3rd byte 4th byte Action
CE (chip PP (Page CP erase) program) (Continuou sly program mode) 38 (hex) 20 (hex) D8 (hex) 60 or C7 02 (hex) AD (hex) (hex) AD1 AD1 AD1 AD1 AD1 AD2 AD2 AD2 AD2 AD3 AD3 AD3 AD3 quad input to erase to erase to erase to continously to program the the whole program program the selected selected selected chip the whole chip, page sector block selected the page address is automatical ly increase
SE (sector erase)
BE (block erase)
DP (Deep power down)
B9 (hex)
RDP (Release from deep power down) AB (hex)
RES (read Read electronic Enhanced ID)
AB (hex) x x x to read out 1-byte device ID
FF (hex) x x x All these commands FFh,00h,AAh or 55h will escape the performance enhance mode.
enters release deep power from deep down mode power down mode
COMM AND RE MS (read RE MS 2 RE MS 4 (byte) electronic (read ID for (read ID for manufacturer 2x I/O mode) 4x I/O mode) & device ID) 1st byte 2nd byte 3rd byte 4th byte Action 90 (hex) x x ADD (Note 2) output the manufacturer ID & device ID E F (hex) x x A DD (Note 2) output the m anufacturer ID & device ID DF (hex) x x A DD (Note 2) output the m anufacturer ID & device ID
E NSO (enter secured OTP) B 1 (hex)
EXS O (exit RDSCUR W RS CUR secured (read (write OTP ) security security register) register) C1 (hex) 2B (hex) 2F (hex)
E S RY (enable S O to output RY /B Y#) 70 (hex)
DS RY (disable S O to output RY /B Y#) 80 (hex)
to enter the 4K -bit secured OTP m ode
to exit the 4K-bit secured OTP m ode
to read value of security register
to set the lock-down bit as "1" (once lock-down, cannot be updated)
to enable S O to output RY /B Y# during CP m ode
to disable S O to output RY /B Y# during CP m ode
Note 1: Note 2: Note 3:
The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O, and the MSB is on SI/SIO1, which is different from 1 x I/O condition. ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first. It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. 15
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(1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, CP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low-> sending WREN instruction code-> CS# goes high. (see Figure 9)
(2) Write Disable (WRDI) The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low-> sending WRDI instruction code-> CS# goes high. (see Figure 10) The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Quad Page Program (4PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE) instruction completion - Chip Erase (CE) instruction completion - Continuously program mode (CP) instruction completion
(3) Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manufacturer ID is C2(hex), the memory type ID is 5E(hex) as the first-byte device ID, and the individual device ID of second-byte ID are listed as table of "ID Definitions". (see table 7 in page 26) The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data out on SO -> to end RDID operation can use CS# to high at any time during data out. (see Figure 11.) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
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(4) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low-> sending RDSR instruction code-> Status Register data out on SO (see Figure 12) The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and not affect value of WEL bit if it is applied to a protected memory area. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed). QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0", it performs non-Quad and WP# is enable. While QE is "1", it performs Quad I/O mode and WP# is disabled. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#/ SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only.
Status Register
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 BP3 SRWD BP2 BP1 BP0 WEL WIP QE (level of (status register (Quad Enable) (level of (level of (level of (write enable (write in write protect) latch) protected block) protected block) protected block) protected block) progress bit) 1= write 1= Quad Enable 1= status operation 1= write enable (note1) (note1) (note1) (note1) register write 0=not Quad 0= not write 0= not in write Enable disable operation enable Non- volatile bit Non- volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit
Note: 1. See the table "Protected Area Sizes". The BP0 & BP1 default values are "1" (protected). 2. The SRWD default value is "0".
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(5) Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as shown in table 1). The WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the statur register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low-> sending WRSR instruction code-> Status Register data on SI-> CS# goes high. (see Figure 13)
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The selftimed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
Table 6. Protection Modes
Mode Software protection mode(SPM) Status register condition Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP3 bits can be changed WP# and SRWD bit status WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 Memory The protected area cannot be program or erase.
Hardware protection mode (HPM)
The SRWD, BP0-BP3 of status register bits cannot be changed
WP#=0, SRWD bit=1
The protected area cannot be program or erase.
Note: 1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 1. As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM): - When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM). - When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM) Note: If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed.
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Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification. Note: To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0. If the system goes into four I/O read mode, the feature of HPM will be disabled. (6) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low-> sending READ instruction code-> 3-byte address on SI -> data out on SO-> to end READ operation can use CS# to high at any time during data out. (see Figure 14)
(7) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low-> sending FAST_READ instruction code-> 3-byte address on SI-> 1-dummy byte (default) address on SI->data out on SO-> to end FAST_READ operation can use CS# to high at any time during data out. (see Figure 15) While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
(8) 2 x I/O Read Mode (2READ) The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits(interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruction, the following address/dummy/ data out will perform as 2-bit instead of previous 1-bit. The sequence of issuing 2READ instruction is: CS# goes low sending 2READ instruction 24-bit address interleave on SIO1 & SIO0 4-bit dummy cycle on SIO1 & SIO0 data out interleave on SIO1 & SIO0 to end 2READ operation can use CS# to high at any time during data out (see Figure 16 for 2 x I/O Read Mode Timing Waveform). While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
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(9) 4 x I/O Read Mode (4READ) The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before seding the 4READ instruction.The address is latched on rising edge of SCLK, and data of every four bits(interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. The sequence of issuing 4READ instruction is: CS# goes low sending 4READ instruction24-bit address interleave on SIO3, SIO2, SIO1 & SIO0 6 dummy cycles data out interleave on SIO3, SIO2, SIO1 & SIO0 to end 4READ operation can use CS# to high at any time during data out (see Figure 17 for 4 x I/O Read Mode Timing Waveform). Another sequence of issuing 4 READ instruction especially useful in random access is : CS# goes low sending 4 READ instruction3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 performance enhance toggling bit P[7:0]4 dummy cycles data out still CS# goes high CS# goes low (reduce 4 Read instruction) 24-bit random access address (see figure 18 for 4x I/O read enhance performance mode timing waveform). In the performance-enhancing mode (Note of Figure. 18), P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h. These commands will reset the performance enhance mode. And afterwards CS# is raised and then lowered, the system then will return to normal operation. While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
(10) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS# goes high. (see Figure 22) The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
(11) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64Kbyte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the
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instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low -> sending BE instruction code-> 3-byte address on SI -> CS# goes high. (see Figure 23) The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.
(12) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low-> sending CE instruction code-> CS# goes high. (see Figure 24) The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3, BP2, BP1, BP0 all set to "0".
(13) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-A0 (The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page. The sequence of issuing PP instruction is: CS# goes low-> sending PP instruction code-> 3-byte address on SI-> at least 1-byte on data on SI-> CS# goes high. (see Figure 19) The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
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(14) 4 x I/O Page Program (4PP) The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3, which can raise programer performance and and the effectiveness of application of lower clock less than 20MHz. For system with faster clock, the Quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 20MHz below. The other function descriptions are as same as standard page program. The sequence of issuing 4PP instruction is: CS# goes low-> sending 4PP instruction code-> 3-byte address on SIO[3:0]> at least 1-byte on data on SIO[3:0]-> CS# goes high. (see Figure 20)
(15) Continuously program mode (CP mode) The CP mode may enhance program performance by automatically increasing address to the next higher address after each byte data has been programmed. The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction must execute to set the Write Enable Latch(WEL) bit before sending the Continuously program (CP) instruction. CS# requires to go high before CP instruction is executing. After CP instruction and address input, two bytes of data is input sequentially from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address range with A0=0 and second byte data with A0=1. If only one byte data is input, the CP mode will not process. If more than two bytes data are input, the additional data will be ignored and only two byte data are valid. The CP program instruction will be ignored and not affect the WEL bit if it is applied to a protected memory area. Any byte to be programmed should be in the erase state (FF) first. It will not roll over during the CP mode, once the last unprotected address has been reached, the chip will exit CP mode and reset write Enable Latch bit (WEL) as "0" and CP mode bit as "0". Please check the WIP bit status if it is not in write progress before entering next valid instruction. During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05 hex), and RDSCUR command (2B hex). And the WRDI command is valid after completion of a CP programming cycle, which means the WIP bit=0. The sequence of issuing CP instruction is : CS# high to low-> sending CP instruction code-> 3-byte address on SI-> Data Byte on SI->CS# goes high to low-> sending CP instruction......-> last desired byte programmed or sending Write Disable (WRDI) instruction to end CP mode-> sending RDSR instruction to verify if CP mode is ended. (see Figure 21 of CP mode timing waveform) Three methods to detect the completion of a program cycle during CP mode: 1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode. 2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not. 3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a program cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is enable in CP mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indicates ready stage, SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the ESRY/DSRY command are not accepted unless the completion of CP mode.
(16) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the
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Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/ Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low-> sending DP instruction code-> CS# goes high. (see Figure 25) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Power-down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
(17) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Powerdown mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. The sequence is shown as Figure 26,27. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Powerdown mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. The RDP instruction is for releasing from Deep Power Down Mode.
(18) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) The REMS, REMS2 & REMS4 instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS, REMS2 & REMS4 instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" or "EFh" or "DFh"followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in figure 31. The Device ID values are listed in Table of ID Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high.
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Table 7. ID Definitions
Command Type Manufacturer ID RDID (JEDEC ID) C2 RES REMS/REMS2/ REMS4 Manufacturer ID C2
MX25L3225D Memory type 5E Electronic ID 5E Device ID 5E
Memory Density 16
(19) Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 4K-bit secured OTP mode. The additional 4K-bit secured OTP is independent from main array, which may use to store unique serial number for system identifier. After entering the Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CS# goes low-> sending ENSO instruction to enter Secured OTP mode -> CS# goes high. Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once security OTP is lock down, only read related commands are valid.
(20) Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 4K-bit secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low-> sending EXSO instruction to exit Secured OTP mode-> CS# goes high.
(21) Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low-> send ing RDSCUR instruction -> Security Register data out on SO-> CS# goes high. The definition of the Security Register bits is as below: Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lockdown purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP area cannot be update any more. While it is in 4K-bit secured OTP mode, array access is not allowed. Continuously Program Mode( CP mode) bit. The Continuously Program Mode bit indicates the status of CP mode, "0" indicates not in CP mode; "1" indicates in CP mode.
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Table 8. Security Register Definition
bit7 x bit6 x bit5 x bit4 Continuously Program mode (CP mode) 0=normal Program mode 1=CP mode (default=0) volatile bit bit3 x bit2 x bit1 bit0 LDSO (indicate if Secrured OTP lock-down indicator bit 0 = not lockdown 0 = non1 = lock-down factory lock (cannot program/erase 1 = factory lock OTP) non-volatile bit non-volatile bit
reserved
reserved
reserved
reserved
reserved
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit
(22) Write Security Register (WRSCUR) The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low-> sending WRSCUR instruction -> CS# goes high. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
P/N: PM1432
25
REV. 0.00, SEP. 19, 2008
MX25L3225D
POWER-ON STATE
The device is at below states when power-up: - Standby mode ( please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device has no response to any command. For further protection on the device, after VCC reaching the VWI level, a tPUW time delay is required before the device is fully accessible for commands like write enable(WREN), page program (PP), Continuously Program (CP), sector erase(SE), chip erase(CE), WRSCUR and write status register(WRSR). If the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The write, erase, and program command should be sent after the below time delay: - tPUW after VCC reached VWI level - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL, even time of tPUW has not passed. Please refer to the figure of "power-up timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.(generally around 0.1uF) - At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress.
P/N: PM1432
26
REV. 0.00, SEP. 19, 2008
MX25L3225D
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential VALUE -40 C to 85 C for Industrial grade -55 C to 125 C -0.5V to 4.6V -0.5V to 4.6V -0.5V to 4.6V
NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot to 4.6V or -0.5V for period up to 20ns. 4. All input and output pins may overshoot to VCC+0.5V while VCC+0.5V is smaller than or equal to 4.6V.
Figure 2.Maximum Negative Overshoot Waveform
Figure 3. Maximum Positive Overshoot Waveform
20ns
0V -0.5V
4.6V 3.6V
20ns
CAPACITANCE TA = 25 C, f = 1.0 MHz SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance MIN. TYP MAX. 6 8 UNIT pF pF CONDITIONS VIN = 0V VOUT = 0V
P/N: PM1432
27
REV. 0.00, SEP. 19, 2008
MX25L3225D
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing referance level 0.8VCC 0.7VCC 0.3VCC 0.2VCC AC Measurement Level
Output timing referance level
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 5. OUTPUT LOADING
DEVICE UNDER TEST
2.7K ohm +3.3V
CL
6.2K ohm
DIODES=IN3064 OR EQUIVALENT
CL=30pF Including jig capacitance (CL=15pF Including jig capacitance for 104MHz, 75MHz@2xI/O and 75MHz@4xI/O)
P/N: PM1432
28
REV. 0.00, SEP. 19, 2008
MX25L3225D
Table 9. DC CHARACTERISTICS (Temperature = -40 C to 85 C for Industrial grade, VCC = 2.7V ~ 3.6V) SYMBOL PARAMETER ILI ILO ISB1 ISB2 ICC1 Input Load Current Output Leakage Current VCC Standby Current Deep Power-down Current VCC Read 1 25 mA 20 uA 1 20 uA 1 2 uA NOTES 1 MIN. TYP MAX. UNITS 2 uA TEST CONDITIONS VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VIN = VCC or GND CS# = VCC VIN = VCC or GND CS# = VCC f=104MHz fQ=75MHz (4 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open 20 mA f=66MHz fT=75MHz (2 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open 10 ICC2 ICC3 VCC Program Current (PP) VCC Write Status Register (WRSR) Current ICC4 ICC5 VIL VIH VOL VOH VCC Sector Erase Current (SE) VCC Chip Erase Current (CE) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VCC-0.2 -0.5 0.7VCC 0.3VCC VCC+0.4 0.4 V V V V IOL = 1.6mA IOH = -100uA 1 20 mA 1 20 mA Erase in Progress CS#=VCC Erase in Progress CS#=VCC 20 mA 1 20 mA mA f=33MHz SCLK=0.1VCC/0.9VCC, SO=Open Program in Progress CS# = VCC Program status register in progress CS#=VCC
Notes : 1. Typical values at VCC = 3.3V, T = 25 C. These currents are valid for all product versions (package and speeds). 2. Typical value is calculated by simulation.
P/N: PM1432
29
REV. 0.00, SEP. 19, 2008
MX25L3225D
Table 10. AC CHARACTERISTICS (Temperature = -40 C to 85 C for Industrial grade, VCC = 2.7V ~ 3.6V) Symbol fSCLK Alt. fC Parameter Clock Frequency for the following instructions: FAST_READ, PP, SE, BE, CE, DP, RES,RDP WREN, WRDI, RDID, RDSR, WRSR Clock Frequency for READ instructions Clock Frequency for 2READ instructions Clock Frequency for 4READ instructions Clock Frequency for 4PP operation Min. D.C. D.C. Typ. Max. Unit 104 MHz (Condition:15pF) 66 MHz (Condition:30pF) 33 MHz 75 MHz 75 MHz (Condition:15pF) 20 MHz (Condition:30pF) ns ns V/ns V/ns ns ns ns ns ns ns ns ns 10 ns 8 ns 10/8 ns 8/6 ns ns ns ns 10 us 8.8 us 8.8 us 40 100 ms 9 300 us 1.4 5 ms 90 300 ms 0.7 2 s 25 50 s
fRSCLK fTSCLK
fR fT fQ fP
fPSCLK tCH(1) tCL(1) tCLCH(2) tCHCL(2) tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL(3) tSHQZ(2) tCLQV
tCLQX tWHSL(4) tSHWL(4) tDP(2) tRES1(2) tRES2(2) tW tBP tPP tSE tBE tCE Notes: 1. tCH + tCL must be greater than or equal to 1/ fC 2. Value guaranteed by characterization, not 100% tested in production. 3. tSHSL=15ns from read instruction, tSHSL=50ns from Write/Erase/Program instruction. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 5. Test condition is shown as Figure 4, 5.
P/N: PM1432
tCLH Clock High Time 5 tCLL Clock Low Time 5 Clock Rise Time (3) (peak to peak) 0.1 Clock Fall Time (3) (peak to peak) 0.1 tCSS CS# Active Setup Time (relative to SCLK) 5 CS# Not Active Hold Time (relative to SCLK) 5 tDSU Data In Setup Time 2 tDH Data In Hold Time 5 CS# Active Hold Time (relative to SCLK) 5 CS# Not Active Setup Time (relative to SCLK) 5 tCSH CS# Deselect Time Read 15 Write/Erase/Program 50 tDIS Output Disable Time 2.7V-3.6V 3.0V-3.6V tV Clock Low to Output Valid 2.7V-3.6V Loading: 30pF/15pF 3.0V-3.6V tHO Output Hold Time 0 Write Protect Setup Time 20 Write Protect Hold Time 100 CS# High to Deep Power-down Mode CS# High to Standby Mode without Electronic Signature Read CS# High to Standby Mode with Electronic Signature Read Write Status Register Cycle Time Byte-Program Page Program Cycle Time Sector Erase Cycle Time Block Erase Cycle Time Chip Erase Cycle Time
30
REV. 0.00, SEP. 19, 2008
MX25L3225D
Timing Analysis
Figure 6. Serial Input Timing
tSHSL CS# tCHSL SCLK tDVCH tCHDX SI MSB tCLCH LSB tCHCL tSLCH tCHSH tSHCH
SO
High-Z
Figure 7. Output Timing
CS# tCH SCLK tCLQV tCLQX SO tQLQH tQHQL SI
ADDR.LSB IN
tCLQV tCLQX
tCL
tSHQZ
LSB
P/N: PM1432
31
REV. 0.00, SEP. 19, 2008
MX25L3225D
Figure 8. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP# tWHSL tSHWL
CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SI
01
SO
High-Z
Figure 9. Write Enable (WREN) Sequence (Command 06)
CS# 0 SCLK Command SI 06 1 2 3 4 5 6 7
SO
High-Z
Figure 10. Write Disable (WRDI) Sequence (Command 04)
CS# 0 SCLK Command SI 04 1 2 3 4 5 6 7
SO
High-Z
P/N: PM1432
32
REV. 0.00, SEP. 19, 2008
MX25L3225D
Figure 11. Read Identification (RDID) Sequence (Command 9F)
CS# 0 SCLK Command SI 9F Manufacturer Identification SO High-Z 7 MSB 6 5 3 2 1 Device Identification 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31
0 15 14 13 MSB
Figure 12. Read Status Register (RDSR) Sequence (Command 05)
CS# 0 SCLK command SI 05 Status Register Out High-Z SO 7 MSB 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 0 7 Status Register Out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 13. Write Status Register (WRSR) Sequence (Command 01)
CS# 0 SCLK command Status Register In 7 MSB 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SI
01
SO
High-Z
P/N: PM1432
33
REV. 0.00, SEP. 19, 2008
MX25L3225D
Figure 14. Read Data Bytes (READ) Sequence (Command 03)
CS# 0 SCLK command 24-Bit Address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SI
03
23 22 21 MSB
3
2
1
0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 7
High-Z SO MSB
Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS# 0 SCLK Command 24 BIT ADDRESS 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SI
0B
23 22 21
3
2
1
0
SO
High-Z
CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Configurable Dummy Cycle
SI
7
6
5
4
3
2
1
0 DATA OUT 1 DATA OUT 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB
SO
7 MSB
6
5
4
3
2
P/N: PM1432
34
REV. 0.00, SEP. 19, 2008
MX25L3225D
Figure 16. 2 x I/O Read Mode Sequence (Command BB)
CS#
0 SCLK
1
2
3
4
5
6
7
8 9 10 11
18 19 20 21 22 23 24 25 26 27
8 Bit Instruction
12 BIT Address
4 dummy cycle
Data Output
SI/SIO0
BB(hex)
address bit22, bit20, bit18...bit0
dummy
data bit6, bit4, bit2...bit0, bit6, bit4....
High Impedance SO/SIO1
address bit23, bit21, bit19...bit1
dummy
data bit7, bit5, bit3...bit1, bit7, bit5....
Figure 17. 4 x I/O Read Mode Sequence (Command EB)
CS#
0 SCLK
1
2
3
4
5
6
7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
8 Bit Instruction
6 Address cycles
6 dummy cycle
Data Output
SI/SIO0
EB(hex)
address bit20, bit16..bit0
dummy
data bit4, bit0, bit4....
High Impedance SO/SIO1
address bit21, bit17..bit1
dummy
data bit5 bit1, bit5....
High Impedance WP#/SIO2
address bit22, bit18..bit2
dummy
data bit6 bit2, bit6....
High Impedance NC/SIO3
address bit23, bit19..bit3
dummy
data bit7 bit3, bit7....
P/N: PM1432
35
REV. 0.00, SEP. 19, 2008
MX25L3225D
Figure 18. 4 x I/O Read enhance performance Mode Sequence (Command EB)
CS#
0 SCLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
n
8 Bit Instruction
6 Address cycles
Performance enhance indicator (Note)
4 dummy cycles
Data Output
SI/SIO0
EB(hex)
address bit20, bit16..bit0
P4 P0
data bit4, bit0, bit4....
High Impedance SO/SIO1
address bit21, bit17..bit1
P5 P1
data bit5 bit1, bit5....
High Impedance WP#/SIO2
address bit22, bit18..bit2
P6 P2
data bit6 bit2, bit6....
High Impedance NC/SIO3
address bit23, bit19..bit3
P7 P3
data bit7 bit3, bit7....
CS# n+1 SCLK
6 Address cycles
Performance enhance indicator (Note)
...........
n+7 ...... n+9
........... n+13
...........
4 dummy cycles
Data Output
SI/SIO0
address bit20, bit16..bit0
P4 P0
data bit4, bit0, bit4....
SO/SIO1
address bit21, bit17..bit1
P5 P1
data bit5 bit1, bit5....
WP#/SIO2
address bit22, bit18..bit2
P6 P2
data bit6 bit2, bit6....
NC/SIO3
address bit23, bit19..bit3
P7 P3
data bit7 bit3, bit7....
Note: Performance enhance mode, if P7=P3 & P6=P2 & P5=P1 & P4=P0 (Toggling), ex: A5, 5A, 0F Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF
P/N: PM1432
36
REV. 0.00, SEP. 19, 2008
MX25L3225D
Figure 19. Page Program (PP) Sequence (Command 02)
CS# 0 SCLK Command 24-Bit Address Data Byte 1 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SI
02
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
2072
2073
2074
2075
2076
2077
2
0 1 2 3
2078
1
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Data Byte 2 Data Byte 3
Data Byte 256
SI
7
6
5
4
3
2
1
0
7 MSB
6
5
4
3
2
1
0
7
6
5
4
3
0
MSB
MSB
Figure 20. 4 x I/O Page Program (4PP) Sequence (Command 38)
CS# 0 SCLK Command 6 Address cycle Data Data Data Data Byte 1 Byte 2 Byte 3 Byte 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
SI/SIO0
38
20 16 12 8
4
4
0
4
0
4
0
4
SO/SIO1
21 17 13 9
5
1
5 6
1 2
5 6
1 2
5 6
1 2
5 6
WP#/SIO2
22 18 14 10
6
2
NC/SIO3
23 19 15 11
7
3
7
3
7
3
7
3
7
P/N: PM1432
37
REV. 0.00, SEP. 19, 2008
2079
MX25L3225D
Figure 21. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD)
CS#
01 6789 30 31 31 32 47 48 01
6 78
20 21 22 23 24
0
7
0
78
SCLK Command SI
AD (hex) 24-bit address data in Byte 0, Byte1 Valid Command (1) data in Byte n-1, Byte n
04 (hex)
05 (hex)
S0
high impedance
status (2)
Note: (1) During CP mode, the valid commands are CP command (AD hex), WRDI command (04 hex), RDSR command (05 hex), and RDSCUR command (2B hex). (2) Once an internal programming operation begins, CS# goes low will drive the status on the SO pin and CS# goes high will return the SO pin to tri-state. (3) To end the CP mode, either reaching the highest unprotected address or sending Write Disable (WRDI) command (04 hex) may achieve it and then it is recommended to send RDSR command (05 hex) to verify if CP mode is ended
Figure 22. Sector Erase (SE) Sequence (Command 20)
CS# 0 SCLK Command 24 Bit Address 1 2 3 4 5 6 7 8 9 29 30 31
SI
20
23 22 MSB
2
1
0
Note: SE command is 20(hex).
Figure 23. Block Erase (BE) Sequence (Command D8)
CS# 0 SCLK Command 24 Bit Address 1 2 3 4 5 6 7 8 9 29 30 31
SI
D8
23 22 MSB
2
1
0
Note: BE command is D8(hex).
P/N: PM1432
38
REV. 0.00, SEP. 19, 2008
MX25L3225D
Figure 24. Chip Erase (CE) Sequence (Command 60 or C7)
CS# 0 SCLK Command SI 60 or C7 1 2 3 4 5 6 7
Note: CE command is 60(hex) or C7(hex).
Figure 25. Deep Power-down (DP) Sequence (Command B9)
CS# 0 SCLK Command SI B9 1 2 3 4 5 6 7 tDP
Stand-by Mode
Deep Power-down Mode
Figure 26. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
CS# 0 SCLK Command 3 Dummy Bytes tRES2 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
SI
AB
23 22 21 MSB
3
2
1
0 Electronic Signature Out 7 MSB Deep Power-down Mode Stand-by Mode 6 5 4 3 2 1 0
High-Z SO
P/N: PM1432
39
REV. 0.00, SEP. 19, 2008
MX25L3225D
Figure 27. Release from Deep Power-down (RDP) Sequence (Command AB)
CS# 0 SCLK Command SI AB 1 2 3 4 5 6 7 tRES1
High-Z SO
Deep Power-down Mode
Stand-by Mode
Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)
CS# 0 SCLK Command 2 Dummy Bytes 1 2 3 4 5 6 7 8 9 10
SI
90
15 14 13
3
2
1
0
SO
High-Z
CS# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK ADD (1)
SI
7
6
5
4
3
2
1
0 Manufacturer ID Device ID 0 7 MSB 6 5 4 3 2 1 0 7 MSB
SO
X
7 MSB
6
5
4
3
2
1
Notes: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first (2) Instruction is either 90(hex) or EF(hex) or DF(hex).
P/N: PM1432
40
REV. 0.00, SEP. 19, 2008
MX25L3225D
Figure 29. Power-up Timing
VCC VCC(max) Program, Erase and Write Commands are Ignored Chip Selection is Not Allowed VCC(min) Reset State of the Flash VWI tPUW tVSL Read Command is allowed Device is fully accessible
time
Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.
Table 11. Power-Up Timing and VWI Threshold Symbol tVSL(1) tPUW(1) VWI(1) Parameter VCC(min) to CS# low Time delay to Write instruction Write Inhibit Voltage Min. 200 1 1.5 Max. 10 2.5 Unit us ms V
Note: 1. These parameters are characterized only.
INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0).
P/N: PM1432
41
REV. 0.00, SEP. 19, 2008
MX25L3225D
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND tVR tSHSL
CS#
tCHSL tSLCH tCHSH tSHCH
SCLK
tDVCH tCHDX tCLCH LSB IN tCHCL
SI
MSB IN
SO
High Impedance
Figure A. AC Timing at Device Power-Up
Symbol tVR
Parameter VCC Rise Time
Notes 1
Min. 20
Max. 500000
Unit us/V
Notes : 1. Sampled, not 100% tested. 2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table.
P/N: PM1432
42
REV. 0.00, SEP. 19, 2008
MX25L3225D
ERASE AND PROGRAMMING PERFORMANCE
PARAMETER Write Status Register Cycle Time Sector Erase Time Block Erase Time Chip Erase Time Byte Program Time (via page program command) Page Program Time Erase/Program Cycle Min. TYP. (1) 40 90 0.7 25 9 1.4 100,000 Max. (2) 100 300 2 50 300 5 UNIT ms ms s s us ms cycles
Note: 1. Typical program and erase time assumes the following conditions: 25 C, 3.3V, and checker board pattern. 2. Under worst conditions of 85 C and 2.7V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. 4. The maximum chip programming time is evaluated under the worst conditions of 0C, VCC=3.0V, and 100K cycle with 90% confidence level.
LATCH-UP CHARACTERISTICS
MIN. Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. -1.0V -1.0V -100mA MAX. 2 VCCmax VCC + 1.0V +100mA
P/N: PM1432
43
REV. 0.00, SEP. 19, 2008
MX25L3225D
ORDERING INFORMATION
PART NO. CLOCK (MHz) 104 OPERATING STANDBY Temperature PACKAGE Remark CURRENT MAX. CURRENT MAX. (mA) (uA) 25 20 -40C~85C 8-SOP Pb-free (200mil)
MX25L3225DM2I-10G
P/N: PM1432
44
REV. 0.00, SEP. 19, 2008
MX25L3225D
PART NAME DESCRIPTION
MX 25
L 3225D
M2
I
10 G
OPTION: G: Pb-free SPEED: 10: 104MHz TEMPERATURE RANGE: I: Industrial (-40 C to 85 C)
PACKAGE: M2: 200mil 8-SOP
DENSITY & MODE: 3225D: 32Mb standard type
TYPE: L: 3V
DEVICE: 25: Serial Flash
P/N: PM1432
45
REV. 0.00, SEP. 19, 2008
MX25L3225D
PACKAGE INFORMATION
P/N: PM1432
46
REV. 0.00, SEP. 19, 2008
MX25L3225D
Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications.
MACRONIX INTERNATIONAL CO., LTD.
Headquarters Macronix, Int'l Co., Ltd.
16, Li-Hsin Road, Science Park, Hsinchu, Taiwan, R.O.C. Tel: +886-3-5786688 Fax: +886-3-5632888
Taipei Office Macronix, Int'l Co., Ltd.
19F, 4, Min-Chuan E. Road, Sec. 3, Taipei, Taiwan, R.O.C. Tel: +886-2-2509-3300 Fax: +886-2-2509-2200
Macronix America, Inc.
680 North McCarthy Blvd. Milpitas, CA 95035, U.S.A. Tel: +1-408-262-8887 Fax: +1-408-262-8810 Email: sales.northamerica@macronix.com
Macronix Europe N.V.
Koningin Astridlaan 59, Bus 1 1780 Wemmel Belgium Tel: +32-2-456-8020 Fax: +32-2-456-8021
Macronix Asia Limited.
NKF Bldg. 5F, 1-2 Higashida-cho, Kawasaki-ku Kawasaki-shi, Kanagawa Pref. 210-0005, Japan Tel: +81-44-246-9100 Fax: +81-44-246-9105
Singapore Office Macronix Pte. Ltd.
1 Marine Parade Central #11-03 Parkway Centre Singapore 449408 Tel: +65-6346-5505 Fax: +65-6348-8096
Macronix (Hong Kong) Co., Limited.
702-703, 7/F, Building 9, Hong Kong Science Park, 5 Science Park West Avenue, Sha Tin, N.T. Tel: +86-852-2607-4289 Fax: +86-852-2607-4229
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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